A comparison of fault-tolerant state machine architectures for space-borne electronics

and Conclusions Very Large Scale Integrated (VLSI) circuits used in the space and nuclear industry are continuously subjected to ion radiation. As the limits of VLSI technology are pushed towards sub-micron levels in order to achieve higher levels of integration devices become more vulnerable to radiation induced errors. These radiation induced errors may lead to possible system failure, particularly if they aaect the memory portion of vital subsystems , such as state machine controllers. 1 This paper explored the use of classical fault-tolerant state machine architectures based on hardware and information redundancy to design radiation-immune controllers. Those ar-chitectures particularly suitable for VLSI-implementation using standard, low power CMOS technology were identiied, with the primary objective of correcting single ip op errors. Each architecture was implemented on a set of benchmark sequential circuits and evaluated in terms of circuit size and maximum path delay. It was found that the best overall architectures, SEU-I TMR and Modiied Explicit EC, used a non-redundant excitation circuit and redundant ip ops, followed by error correction circuitry to tolerate single ip op errors.